The present invention generally relates to direct memory access (DMA) controllers, and more particularly to a direct memory access controller for controlling a direct memory access in which data is transferred directly between a memory device and an input/output device at a high speed during a time when a central processing unit forfeits exclusive right to a system bus of a data processing apparatus having the central processing unit.
Conventionally, a DMA controller controls a data transfer in conformance with a DMA by microprograms or a random logic. However, the conventional DMA only requires relatively simple control of the address and control of the byte for determining a byte to which an access is to be made because a bit length of the data transfer is eight or sixteen bits which is relatively small. For this reason, a decrease in a data transfer speed due to the use of the microprograms for the DMA control and an increase in the hardware due to the use of the random logic for the DMA control do not cause serious problems.
But in recent DMA, the bit length of the data transfer is becoming large such as thirty-two bits. As a result, the address control, the byte control, and a control of the generation of control signals for carrying out these controls are becoming extremely complex. When combinations of port size, operand size, misalignment and the like are considered, a DMA controller for controlling a DMA with a bit length of thirty-two bits must control over four thousand different combinations of data transfers. The port size in this case means the physical bit length of peripheral input/output devices, and the operand size means a logical bit length of the peripheral input/output devices.
Accordingly, when the bit length of the data transfer is large such as thirty-two bits, for example, the use of the microprograms for the DMA control results in a large number of program steps because of complex condition discriminations and there is a problem in that the data transfer speed becomes slow since it takes considerable time to make the condition discriminations. On the other hand, when the random logic is used for the DMA control, the scale of the hardware becomes extremely large and there is a problem in that it is very difficult to correct the logic when an error exists in the logic design.
FIG. 1 shows an essential part of a conventional DMA controller which uses microprograms for the DMA control. The, conventional DMA controller includes a request controller 10, a microsequencer 11 which stores microprograms, an address register 12, and a bus controller 13.
When a transfer request is received at the request controller 10 through a terminal 14, the bus controller 13 outputs through a terminal 15 a signal for controlling a system bus (not shown) such as a read/write signal responsive to an instruction from the request controller 10. On the other hand, the address register 12 outputs an address through a terminal 16 responsive to the instruction from the request controller 10 and generates a next address by a count-up operation. The microsequencer 11 generates and outputs an information for controlling the data transfer responsive to the request from the request controller 10.
According to this conventional DMA controller, it is necessary to freely control a count-up value of the address register 12. However, the control of the count-up value becomes complex especially when the bit length of the data transfer is large, and there is a problem in that the number of program steps further increases when this control is carried out by the microsequencer 11.